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1 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 general description EM73962 is an advanced single chip cmos 4-bit micro-controller. it contains 16k-byte rom, 372-nibble ram, 4-bit alu, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernal function. EM73962 also contains 5 interrupt sources, 3 i/o ports (including 1 input port and 2 bidirection ports), lcd display (40x8), built-in sound generator. except low-power consumption and high speed, EM73962 also have a sleep mode for power saving function. EM73962 is suitable for appliaction in many fields, for example : family appliance, consumer products, hand held games and the toy controller ... etc. features ? operation voltage : 2.4v to 5.0v. ? clock source : single clock system for both rc and crystal is available by mask option. external clock and internal clock is available by mask option. ? oscillation frequency : 480k, 1m, 2m and 4m hz is available by mask option. ? instruction set : 107 powerful instructions. ? instruction cycle time : up to 2us for 4 mhz. ? rom capacity : 16384 x 8 bits. ? ram capacity : 372 x 4 bits. ? input port : 1 port (p0.0-p0.3) and sleep/hold releasing function are available by mask option. (each input pin is pull-up and pull-down resistor available by mask option). ? bidirection port : 2 ports (p4, p8). p4.0 and sound is available by mask option. p8(0..3) and sleep/ hold releasing function are available by mask option. ? 12-bit timer/counter : two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement. ? built-in time base counter : 22 stages. ? subroutine nesting : up to 13 levels. ? interrupt : external . . . . . 2 input interrupt sources. internal . . . . . . 2 timer overflow interrupts. 1 time base interrupt. ? lcd driver : 40 x 8 dots, 1/8 duty, lcd bias is 1/4 and 1/5 available by mask option, lcd bias resistor is 20k x 5 and 10k x 5 available by mask option. ? sound effect : tone generator, random generator and volume control. ? power saving function :sleep mode and hold mode. ? package type : EM73962h chip form 68 pins. patent number : 61007 (r.o.c) patent pending : 83216083 (r.o.c)
2 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 function block diagram pin descriptions interrupt control time base timer/counter (ta,tb) system control instruction decoder instruction register rom pc data bus reset control clock generator timing generator sleep mode control data pointer acc alu flag zc s stack pointer stack rom hr lr i/o control p0.0/wakeup0 p0.1/wakeup1 p0.2/wakeup2 p0.3/wakeup3 p4.0/sound p4.1 p4.2 p4.3 p8.0(int1)/wakeupa p8.1(trgb)/wakeupb p8.2(int0)/wakeupc p8.3(trga)/wakeupd reset xin/clk xout/nc sound gen. lcd driver vrlc com0~com7 sound seg0~seg39 symbol pin-type function v dd power supply (+) v ss power supply (-) reset reset-a system reset input signal, low active mask option : none pull-up xin/clk osc-a/osc-c crystal/rc or external clock source connecting pin xout/nc osc-a/osc-c crystal/rc connecting pin p0.(0..3)/wakeup0..3 input-b 4-bit input port with sleep/hold releasing function mask option : wakeup enable, pull-up wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none p4.0/sound i/o-o 1-bit bidirection i/o port or inverse sound effect output mask option : sound enable, push-pull, high current pmos sound disable, open-drain sound disable, push-pull, high current pmos sound disable, push-pull, low current pmos p4(1..3) i/o-n 3-bit bidirection i/o port with high current source. mask option : open-drain push-pull, high current pmos push-pull, low current pmos p8.0(int1)/wakeupa i/o-l 2-bit bidirection i/o port with external interrupt sources input and sleep p8.2(int0)/wakeupc /hold releasing function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain
3 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 . . . scall, subroutine call entry address data table for [ldax],[ldaxi] instruction subroutine call entry address designated by [lcall a] instruction function descriptions program rom ( 16k x 8 bits ) for EM73962 16 k x 8 bits program rom contains users program and some fixed data . . . . the basic structure of program rom can be divided into 4 parts. 1. address 0000h: reset start address. 2. address 0002h - 000ch : 5 kinds of interrupt service routine entry addresses . 3. address 000eh-0086h : scall subroutine entry address, only available at 000eh,0016h,001eh,0026h, 002eh, 0036h, 003eh, 0046h, 004eh, 0056h, 005eh, 0066h, 006eh, 0076h, 007eh, 0086h . 4. address 0000h - 07ffh : lcall subroutine entry address. 5. address 0000h - 1fffh : except used as above function, the other region can be used as users program region. address bank 0 : 0000h reset start address 0002h int0; interrupt service routine entry address 0004h 0006h trga 0008h trgb 000ah tbi 000ch int1 000eh 0086h 07ffh 0800h 0fffh 1000h bank 1 1fffh bank 2 bank 3 p8.1(trgb)/wakeupb i/o-l 2-bit bidirection i/o port with time/counter a,b external input and sleep p8.3(trga)/wakeupd /hold releasing function mask option : wakeup enable, push-pull wakeup disable, push-pull wakeup disable, open-drain sound built-in sound effect output vrlc lcd regulator voltage input com0~com7 lcd common output pins seg0~seg39 lcd segment output pins test test pin must be connected to v ss symbol pin-type function
4 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 users program and fixed data are stored in the program rom. users program is according the pc value to send next executed instruction code . the 16kx8 bits program rom can be divided into 4 banks. there are 4kx8 bits in each bank. the bank of the program rom is selected by p3(1..0). the program counter is a 13-bit binary counter. the pc and p3 are initialized to "0" during reset. when p3(1..0)=00b, the bank0 and bank1 of program rom will be selected. p3(1..0)=01b, the the bank0 and bank2 will be selected. p3(1..0)=01b, the bank0 and bank3 will be selected. address p3=xx00b p3=xx01b p3=xx10b 0000h : : bank0 bank0 bank0 0fffh 1000h : : bank1 bank2 bank3 1fffh program example: bank 0 start: : : : ldia #00h ; set program rom to bank1 outa p3 b xa1 : xa : : : ldia #01h ; set program rom to bank2 outa p3 b xb1 : xb : : : ldia #02h ; set program rom to bank3 outa p3 b xc1 : xc : : : bxd xd : : : : ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bank 1 xa1 : : : bxa : xa2 : :
5 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 b xa2 : ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bank 2 xb1 : : : bxb : xb2 : : b xb2 : ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - bank 3 xc1 : : : bxc : xc2 : : b xc2 fixed data can be read out by table-look-up instruction. table-look-up instruction is depended on the data pointer (dp) to rom address, then to get the rom code data : ldax acc ? rom[dp] l ldaxi acc ? rom[dp] h ,dp+1 dp is a 12-bit data register which can store the program rom address to be the pointer for the rom code data. first, user load rom address into dp by instruction "ldadpl, ldadpm, ldadph", then user can get the lower nibble of rom code data by instruction "ldax" and higher nibble by instruction "ldaxi" program example: read out the rom code of address 1777h by table-look-up instruction. ldia #07h; stadpl ; [dp] l ? 07h stadpm ; [dp] m ? 07h stadph ; [dp] h ? 07h, load dp=777h : ldl #00h; ldh #03h; ldax ; acc ? 6h stami ; ram[30] ? 6h ldaxi ; acc ? 5h stam ; ram[31] ? 5h ; org 1777h data 56h; data ram ( 372-nibble ) there is total 372 - nibble data ram from address 000 to 17fh data ram includes 3 parts: zero page region, stacks and data area.
6 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 zero- page: from 000h to 00fh is the location of zero-page . it is used as the pointer in zero -page addressing mode for the instruction of "std #k,y; add #k,y; clr y,b; cmp y,b". program example: to wirte immediate data "07h" to address "003h" of ram and to clear bit 2 of ram. std #07h, 03h ; ram[03] ? 07h clr 0eh,2 ; ram[0eh] 2 ? 0 stack: there are 13 - level ( maximum ) stack for user using for subroutine ( including interrupt and call). user can assign any level be the starting stack by giving the level number to stack pointer( sp) . when user using any instruction of call or subroutine, before entry the subroutine, the previous pc address will be saved into stack until return from those subroutines ,the pc value will be restored by the data saved in stack. data area: except the special area used by user, the whole ram can be used as data area for storing and loading general data. addressing mode the 372 nibble data memory consists of two banks (bank 0 and bank 1). there are 244x4 bits (address 000h~0f3h) on bank 0 and 128x4 bits (address 100h~17fh) on bank 1. increment address 020h - 02fh 0c0h - 0cfh 0d0h - 0dfh 0e0h - 0efh level 0 level 4 level 8 level 12 level 1 level 5 level 9 level 2 level 6 level 10 level 3 level 7 level 11 increment zero-page 000h - 00fh 010h - 01fh 0f0h - 0f3h : : : 110h - 11fh 160h - 16fh 170h - 17fh 100h - 10fh : : : bank 0 bank 1
7 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 there are three addressing modes in the data memory : (1) indirect addressing mode: the bank is selected by p9.3. when p9.3 is cleared to "0", the bank 0 is selected. when p9.3 is set to "1", the bank 1 is selected. the address in the bank are specified by the hl registers. program example: load the data of ram address "143h" to ram address "023h". sep p9,3 ; p9.3 ? 1 ldl #3h ; lr ? 3 ldh #4h ; hr ? 4 ldam ; acc ? ram[134h] clp p9,3 ; p9.3 ? 0 ldl #2h ; lr ? 2 ldh #3h ; hr ? 3 stam ; ram[023h] ? acc (2) direct addressing mode: the bank is selected by p9.3. when p9.3 is cleared to "0", the bank 0 is selected. when p9.3 is set to "1", the bank 1 is selected. the address in the bank are directly specified by 8 bits of the second byte in the instruction field. program example: load the data of ram address "143h" to ram address "023h". sep p9,3 ; p9.3 ? 1 lda 43h ; acc ? ram[134h] clp p9,3 ; p9.3 ? 0 sta 23h ; ram[023h] ? acc (3) zero-page addressing mode: the zero-page is the bank 0 (address 000h~00fh). the address are the lower 4 bits of the second byte in the instruction field. program example: write immediate "0fh" to ram address "005h". std #0fh, 05h ; ram[05h] ? 0fh p9.3 hr lr ram address p9.3 instruction field ram address xxxx xxxx xxxx xxxx 0 instruction field ram address yyyy 0000 yyyy
8 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 +2 program counter (16k rom) for EM73962 program counter ( pc ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program rom. for a 8k - byte size rom, pc can indicate address form 0000h - 1fffh, for branch and call instrcutions, pc is changed by instruction indicating. (1) branch instruction: sbr a object code: 00aa aaaa condition: sf=1; pc ? pc 12-6.a ( branch condition satisified ) pc hold original pc value+1 aaaaaa sf=0; pc ? pc +1( branch condition not satisified) pc original pc value + 1 lbr a object code: 1100 aaaa aaaa aaaa condition: sf=1; pc ? pc 12.a ( branch condition satisified ) pc hold a a a a a aaaaaaa sf=0; pc ? pc +2( branch condition not satisified) pc original pc value + 2 slbr a object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1fffh) 0101 0111 1100 aaaa aaaa aaaa (a:0000h~0fffh) condition: sf=1; pc ? a ( branch condition satisified) pcaaaaaaaaaaaa a sf=0 ; pc ? pc + 3 ( branch condition not satisified ) pc original pc value + 3 (2) subroutine instruction: scall a object code: 1110 nnnn condition : pc ? a ; a=8n+6 ; n=1..fh ; a=86h, n=0 pc00000 aaaaa11 0 lcall a object code: 0100 0aaa aaaa aaaa condition: pc ? a
9 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 pc00aaaaaaaaaa a ret object code: 0100 1111 condition: pc ? stack[sp]; sp + 1 pc the return address stored in stack rt i object code: 0100 1101 condition : flag. pc ? stack[sp]; ei ? 1; sp + 1 pc the return address stored in stack (3) interrupt acceptance operation: when an interrupt is accepted, the original pc is pushed into stack and interrupt vector will be loaded into pc,the interrupt vectors are as following: int0 (external interrupt from p8.2) pc00000000000 1 0 trga (timer a overflow interrupt) pc0000000000 1 1 0 trgb (time b overflow interrupt) pc00000000 0 1 0 0 0 tbi (time base interrupt) pc00000000 0 1 0 1 0 int1 (external interrupt from p8.0) pc00000000 0 1 1 0 0 (4) reset operation: pc00000000000 0 0 (5) other operations: for 1-byte instruction execution: pc + 1 for 2-byte instruction execution: pc + 2 for 3-byte instruction execution: pc + 3
10 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 accumulator accumulator is a 4-bit data register for temporary data . for the arithematic, logic and comparative opertion .., acc plays a role which holds the source data and result . flags there are three kinds of flag, cf ( carry flag ), zf ( zero flag ), sf ( status flag ), these 3 1-bit flags are affected by the arithematic, logic and comparative .... operation . all flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after rti instruction executed . (1) carry flag ( cf ) the carry flag is affected by following operation: a. addition : cf as a carry out indicator, when the addition operation has a carry-out, cf will be "1", in another word, if the operation has no carry-out, cf will be "0". b. subtraction : cf as a borrow-in indicator, when the subtraction operation must has a borrow, in the cf will be "0", in another word, if no borrow-in, cf will be "1". c. comparision: cf is as a borrow-in indicator for comparision operation as the same as subtraction operation. d. rotation: cf shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. cf test instruction : for tfcfc instruction, the content of cf sends into sf then clear itself "0". for ttsfc instruction, the content of cf sends into sf then set itself "1". (2) zero flag ( zf ) zf is affected by the result of alu, if the alu operation generate a "0" result, the zf will be "1", otherwise, the zf will be "0". (3) status flag ( sf ) the sf is affected by instruction operation and system status . a. sf is initiated to "1" for reset condition . b. branch instruction is decided by sf, when sf=1, branch condition will be satisified, otherwise, branch condition will not be satisified by sf = 0 . program example: check following arithematic operation for cf, zf, sf cf zf sf ldia #00h; - 1 1 ldia #03h; - 0 1 adda #05h; - 0 1 adda #0dh; - 0 0 adda #0eh; - 0 0
11 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 alu the arithematic operation of 4 - bit data is performed in alu unit . there are 2 flags can be affected by the result of alu operation, zf and sf . the operation of alu can be affected by cf only . alu structure alu supported user arithematic operation function, including : addition, subtraction and rotaion. alu function (1) addition: for instruction addam, adcam, addm #k, add #k,y .... alu supports addition function. the addition operation can affect cf and zf. for addition operation, if the result is "0", zf will be "1", otherwise, not equal "0", zf will be "0", when the addition operation has a carry-out. cf will be "1", otherwise, cf will be "0". example: operation carry zero 3+4=7 0 0 7+f=6 1 0 0+0=0 0 1 8+8=0 1 1 (2) subtraction: for instruction subm #k, suba #k, sbcam, decm... alu supports user subtraction function . the subtraction operation can affect cf and zf, for subtraction operation, if the result is negative, cf will be "0", it means a borrow out, otherwise, if the result is positive, cf will be "1". for zf, if the result of subtraction operation is "0", the zf will be "1", otherwise, zf will be "1". example: operation carry zero 8-4=4 1 0 7-f= -8(1000) 0 0 9-9=0 1 1 zf cf sf alu data bus
12 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 (3) rotation: there are two kinds of rotation operation, one is rotation left, the other is rotation right. rlca instruction rotates acc value to left, shift the cf value into the lsb bit of acc and the shift out data will be hold in cf. rrca instruction operation rotates acc value to right, shift the cf value into the msb bit of acc and the shift out data will be hold in cf. program example: to rotate acc right and shift a "1" into the msb bit of acc . ttcfs; cf ? 1 rrca; rotate acc right and shift cf=1 into msb. hl register hl register are two 4-bit registers, they are used as a pair of pointer for the address of ram memory and also 2 independent temporary 4-bit data registers. for some instruction, l register can be a pointer to indicate the pin number ( port4 ) . hl register structure hl register function (1) for instruction : ldl #k, ldh #k, tha, thl, incl, decl, exal, exah, hl register used as a temporary register . program example: load immediate data "5h" into l register, "dh" into h register. ldl #05h; ldh #0dh; (2) for instruction ldam, stam, stami .., hl register used as a pointer for the address of ram memory. program example: store immediate data #ah into ram of address 35h. acc cf msb lsb 3 2 1 0 h register 3 2 1 0 l register acc cf msb lsb
13 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 ldl #5h; ldh #3h; stdmi #0ah; ram[35] ? ah (3) for instruction : selp, clpl, tfpl, l regieter be a pointer to indicate the bit of i/o port. when lr = 0 indicate p4.0 program example: to set bit 0 of port4 to "1" ldl #00h; sepl ; p4.0 ? 1 stack pointer (sp) stack pointer is a 4-bit register which stores the present stack level number. before using stack, user must set the sp value first, cpu will not initiate the sp value after reset condition . when a new subroutine is accepted, the sp will be decreased one automatically, in another word, if returning from a subroutine, the sp will be increased one . the data transfer between acc and sp is by instruction of "ldasp" and "stasp". data pointer (dp) data pointer is a 12-bit register which stores the address of rom can indicate the rom code data specified by user (refer to data rom). clock and timing generator the clock generator is supported by a single clock system, the clock source comes from crystal (resonator) or rc oscillation is decided by mask option, the working frequency range is 480 k hz to 4 mhz depending on the working voltage. clock and timing generator structure the clock generator connects outside compoments ( crystal or resonator by xin and xout pin for crystal osc. type, resistor and capacitor by clk pin for rc osc type, these two type is decided by mask option). the clock generator generates a basic system clock "fc". when cpu sleeping, the clock generator will be stoped until the sleep condition released. the system clock control generates 4 basic phase signals ( s1, s2, s3, s4 ) and system clock . clock and timing generator function the frequency of fc is the oscillation frequency for xin, xout by crystal ( resonator) or for clk by rc osc. xin/clk xout crystal connection xin/clk xout rc connection sleep xin/clk xout clock generator system clock control fc system clock s1 s2 s3 s4 mask option mask option for choose crystal or rc oscillation
14 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 when cpu sleeps, the xout pin will be in "high" state . when user choose rc osc, xout pin is no used. the instruction cycle equal 8 basic clock fc. 1 instructure cycle = 8 / fc timing generator and time base the timing generator produces the system clock from basic clock pulse which can be normal mode or slow mode clock. 1 instruction cycle = 8 basic clock pulses there are 22 stages time base . when working in the single clock mode, the timebase clock source is come from fc. time base provides basic frequency for following function: 1. tbi (time base interrupt) . 2. timer/counter, internal clock source. 3. warm-up time for sleep - mode releasing. time base interrupt (tbi ) the time base can be used to generate a fixed frequency interrupt . there are 8 kinds of frequencies can be selected by setting "p25" single clock mode p25 3 2 1 0 ( initial value 0000 ) 0 0 x x: interrupt disable 0 1 0 0: interrupt frequency xin / 2 10 hz 0 1 0 1: interrupt frequency xin / 2 11 hz 0 1 1 0: interrupt frequency xin / 2 12 hz 0 1 1 1: interrupt frequency xin / 2 13 hz 1 1 0 0: interrupt frequency xin / 2 9 hz 1 1 0 1: interrupt frequency xin / 2 8 hz 1 1 1 0: interrupt frequency xin / 2 15 hz 1 1 1 1: interrupt frequency xin / 2 17 hz 1 0 x x: reserved timer / counter ( timera, timerb) timer/counters can support user three special functions: 1. even counter 2. timer. 3. pulse-width measurement. these three functions can be executed by 2 timer/counter independently. for timera, the counter data is saved in timer register tah, tam, tal, which user can set counter initial value and read the counter value by instruction "ldatah(m,l), statah(m,l)" and timer register is tbh, tbm, tbl and w/r instruction "ldatbh (m,l), statbh (m,l)". fc prescaler binary counter 12 3 4 5678910111213 22 21 20 19 18 17 16 15 14
15 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 the basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, p28 and p29 are the command ports for timera and timer b, user can choose different operation mode and different internal clock rate by setting these two ports. when timer/counter overflow, it will generate a trga(b) interrupt request to interrupt control unit. timer/counter control p8.1/trgb, p8.3/trga are the external timer inputs for timerb and timera, they are used in event counter and pulse-width measurement mode. timer/counter command port: p28 is the command port for timer/countera and p29 is for the timer/ counterb. port 28 3 2 1 0 tmsa ipsa initial state: 0000 timer/counter mode selection tmsa (b) function description 0 0 stop 0 1 event counter mode 1 0 timer mode 1 1 pulse width measurement mode port 29 3 2 1 0 tmsb ipsb initial state: 0000 interrupt control trga request p8.3/ trga event counter control timer control internal clock p28 12 bit counter tmsa ipsa data bus p8.1/ trgb event counter control timer control internal clock p29 12 bit counter tmsb ipsb trgb request pulse-width measurement control pulse-width measurement control internal pulse-rate selection ipsa(b) function description 0 0 xin/2 hz 0 1 xin/2 hz 1 0 xin/2 hz 1 1 xin/2 hz 10 14 18 22
16 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 timer/counter function timer/countera can be programmable for timer, event counter and pulse width measurement. each timer/ counter can execute any one of these functions independly. event counter mode for event counter mode, timer/counter increases one at any rising edge of p8.1/trgb for timerb (p8.3/ trga for timer a). when timerb (timera) counts overflow, it will give interrupt control an interrupt request trgb (trga). program example: enable timera with p28 ldia #0100b; outa p28; enable timera with event counter mode timer mode for timer mode ,timer/counter increase one at any rising edge of internal pulse . user can choose 4 kinds of internal pulse rate by setting ipsb for timerb (ipsa for timera). when timer/counter counts overflow, trgb (trga) will be generated to interrupt control unit. program example: to generate trga interrupt request after 60 ms with system clock xln=4mhz ldia #0100b; exae; enable mask 2 eicil 110111b; interrupt latch ? 0, enable ei ldia #06h; statal; ldia #01h; statam; ldia #0fh; statah; ldia #1000b; outa p28; enable timera with internal pulse rate: xin/2 10 hz note: the preset value of timer/counter register is calculated as following procedure. internal pulse rate: xin/2 10 ; xin = 4mhz the time of timer counter count one = 2 10 /xin = 1024/4000=0.256ms the number of internal pulse to get timer overflow = 60 ms/ 0.256ms = 234.375 = 0eah the preset value of timer/counter register = 1000h - 0eah = 0f16h pulse width measurement mode internal pulse timerb (timera )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7 p8.1/trgb (p8.3/trga) timerb (timera) value n n+1 n+2 n+3 n+4 n+5 n+6
17 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 for the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as external timer/counter input (p8.1/trgb, p8.3/trga ), interrupt request will be generated as soon as timer/counter count overflow. internal pulse timerb(timera) value n n+1 n+2 n+3 n+4 n+5 p8.1/trgb(p8.3/trga) program example: enable timera by pulse width measurement mode . ldia #1100b; outa p28; enable timera with pulse width measurement mode. interrupt function there are 5 interrupt sources, 2 external interrupt sources, 3 internal interrupt sources . multiple interrupts are admitted according the priority . type interrupt source priority interrupt interrupt program rom latch enable condition entry address external external interrupt(int0) 1 il5 ei=1 002h internal reserved 2 il4 ei=1, mask3=1 004h internal timera overflow interrupt (trga) 3 il3 ei=1, mask2=1 006h internal timerb overflow interrupt (trgb) 4 il2 ei=1, mask1=1 008h internal time base interrupt(tbi) 5 il1 00ah external external interrupt(int1) 6 il0 ei=1,mask0=1 00ch interrupt structure reset by system reset and program instruction mask0 mask1 mask1 mask2 mask3 il0 int1 r0 il1 tbi r1 il2 r2 il3 trga r3 il4 r4 il5 int0 r5 priority checker ei entry address generator interrupt request interrupt entry address reset by system reset and program instruction set by program instruction trgb interrupt controller: il0-il5 : interrupt latch . hold all interrupt requests from all interrupt sources. ilr can not be set by program, but can be reset by program or system reset, so il only can decide which interrupt source can be accepted. mask0-mask3 : except int0 ,mask register can promit or inhibit all interrupt sources.
18 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 ei : enable interrupt flip-flop can promit or inhibit all interrupt sources, when inter- rupt happened, ei is cleared to "0" automatically, after rti instruction happened, ei will be set to "1" again . priority checker: check interrupt priority when multiple interrupts happened. interrupt function the procedure of interrupt operation: 1. push pc and all flags to stack. 2. set interrupt entry address into pc. 3. set sf= 1. 4. clear ei to inhibit other interrupts happened. 5. clear the il for which interrupt source has already be accepted. 6. to excute interrupt subroutine from the interrupt entry address. 7. cpu accept rti, restore pc and flags from stack . set ei to accept other interrupt requests. program example: to enable interrupt of "int0, trga" ldia #1100b; exae; set mask register "1100b" eicil 111111b ; enable interrupt f.f. power saving function ( sleep / hold functlon ) during sleep and hold condition, cpu holds the systems internal status with a low power consumption, for the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for the stability of system clock running after wakeup . in the other way, for the hold mode, the system clock does not stop at all and it does not need a warm-up time any way. the sleep and hold mode is controlled by port 16 and released by p0(0..3)/wakeup0..3 or p8(0..3)/ wakeupa..d. sleep and hold condition: 1. osc stop ( sleep only ) and cpu internal status held . 2. internal time base clear to "0". p16 3 2 1 0 initial value :0000 swwt set wake-up warm-up time 2 /xin 2 /xin 2 /xin hold mode se enable sleep/hold 0 reserved 1 enable sleep / hold rnode 0 1 wake-up in edge release mode wake-up in level release mode 0 0 0 1 1 0 1 1 18 14 16 wm se swwt wm set wake-up release mode 3. cpu internal memory ,flags, register, i/o held original states. 4. program counter hold the executed address after sleep release. release condition: 1. osc start to oscillating.(sleep only). 2. warm-up time passing ( sleep only ). 3. according pc to execute the following program.
19 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 there is one kind of sleep/hold release mode . 1. edge release mode: release sleep/hold condition by the falling edge of any one of p0(0..3)/wakeup0..3 or p8(0..3)/ wakeupa..d. note : there are 8 independent mask options for wakeup function in EM73962. so, the wakeup function of p0(0..3)/wakeup0..3 and p8(0..3)/wakeupa..d are enabled or disabled independently. lcd driver it can directly drive the liquid crystal display ( lcd ) and has 40 segments , 8 commons output pins. there are total 40x8 dots can be display. the vrlc pin is the lcd driver power input, there is the voltage of ( vcc - vrlc ) to lcd . (1) lcd driver control command register: port27 3210 initial value: 0h ldc * * lcd display control ldc function description 0 0 lcd display disable 0 1 blanking, change common pin output 1 0 reserved 1 1 lcd display enable * : dont care . p27 is the ldc driver control command register . the initial value is 0000 . when ldc ( bit2 and bit3 of p27 ) is set to 00, the lcd display is disabled . when ldc is set to 01, the lcd is blanking, the com pins are inactive and the seg pins continuously output the display data . the power switch of lcd driver is turned off when the cpu is reseted . when ldc is set to 11, the lcd display is enabled, the power switch is turned on and it can not be turned off forever except the cpu is reseted again . the power switch is also turned off during the sleep operation . users must enable the lcd display again by self when the cpu is waked up . (2) lcd display data area: the lcd display data is stored in the display data area of the data memory ( ram) . the display data area begins with address 20h during reset . the lcd display data area is as below: com0 com1 com2 com3 com4 com5 com6 com7 20h 30h 40h 50h 60h 70h 80h 90h b i t 0 b i t 1 b i t 2 b i t 3 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 1 6 s e g 1 7 s e g 1 8 s e g 1 9 s e g 2 0 s e g 2 1 s e g 2 2 s e g 2 3 s e g 2 4 s e g 2 5 s e g 2 6 s e g 2 7 s e g 2 8 s e g 2 9 s e g 3 0 s e g 3 1 s e g 3 2 s e g 3 3 s e g 3 4 s e g 3 5 s e g 3 6 s e g 3 7 s e g 3 8 s e g 3 9 0 1 2 3456 789ab cdef ram
20 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 read automatically the display data from the display data area and send to the lcd driver by the hardware . therefore, the display patterns can be changed only by overwritting the contents of the display data area with the software . the data memory which is not used to store the lcd display data and the addresses are not connected to the lcd can be used to store the ordinary users processing data . program example: ldia #1100b ; lcd display enable outa p27 ldia #1010b sta 24h (3) lcd waveform : (1/5 bias) : on : off com0 com0 com1 com7 seg0 seg0-com0 vdd v4 v3 v2 v1 vrlc com0 vdd v4 v3 v2 v1 vrlc com1 seg0 on com0 com1 seg0 seg0-com0 vdd v3 v2 v1 vrlc com0 vdd v3 v2 v1 vrlc com1 com1 on seg0-com0 off seg0-com0 on seg0-com1 on seg0-com0 on seg0-com1 off seg0-com1 off frame freq.=65hz frame freq.=65hz frame freq. =65hz frame freq. =65hz * type a, 1/4 bias : * type b, 1/4 bias : * type a, modify 1/4 bias : * type b, modify 1/4 bias : bias vdd/(vdd-vrlc) v4/(vdd-vrlc) v3/(vdd-vrlc) v2/(vdd-vrlc) v1/(vdd-vrlc) vrlc/(vdd-vrlc) modify 1/4 1 17/23 12/23 11/23 6/23 0 1/4 1 3/4 1/2 1/4 0 s e g 0 (3) lcd waveform :
21 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 sound effect EM73962 has a built-in sound generator. it includes the tone generator, random generator and volume control. the tone generator is a binary down counter and the random generator is a 9-bit linear feedback shift register. when the cpu is reseted or sleeping, the sound generator is disabled and the output (p4.0/sound) is high . low pwm volume control ? ? fb f1 f2x2 p23,p24 p17 sound p.30 output control tone generator random generator 3 kinds of divider tone frequency register the 8-bit tone frequency register is p24 and p23. the tone frequency will be changed when user output the different data to p23. thus, the data must be output to p24 before p23 when user want to change the 8-bit tone frequency (tf). port24 port23 3 2 1 0 3 2 1 0 initial value : 1111 1111 higher nibble register lower nibble register ** f1=240k/2 x , f2=f1/(tf+1)/2, tf=1~255, tf 1 0 ** example : bfreq=10, tf=00110001b. t f1=60k hz, f2=60k hz/50/2=600 hz random generator f(x)=x 9 +x 4 +1 port30 3 2 1 0 bfreq smode initial value : 0000 bfreq basic frequency (f1) select smode sound generator mode 0 0 240 khz 0 0 disable 0 1 120 khz 0 1 tone output 1 0 60 khz 1 0 random output 1 1 don't care 1 1 tone+random output there are 3 kinds of basic frequency for sound generator which can be selected by p30. the output of sound effect is tone and random combination. sound generator command register 123456789 +
22 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 volume control register the are 8 levels of volume for sound generator. p17 is the volume control register. port17 initial value : * 1111 3 2 1 0 * vcr vcr ts/tp 1 1 1 8/8 1 1 0 7/8 1 0 1 6/7 1 0 0 5/8 0 1 1 4/8 0 1 0 3/8 0 0 1 2/8 0 0 0 1/8 tp ts tp= 60khz 1 program example: ldia #1001b ; basic frequency : 60 khz tone output outa p30 ldia #0011b ; 600 hz tone output outa p24 ldia #0001b outa p23 resetting function when cpu in normal working condition and reset pin holds in low level for three instruction cycles at least, then cpu begins to initialize the whole internal states, and when reset pin changes to high level, cpu begins to work in normal condition. the cpu internal state during reset condition is as following table : hardware condition in reset (f1) state initial value program counter 0000h status flag 01h interrupt enable flip-flop ( ei ) 00h mask0 ,1, 2, 3 00h interrupt latch ( il ) 00h p3, p9, 16, 25, 27, 28, 29, 30 00h p4, 8, 17, 23, 24 0fh xin start oscillation the reset pin is a hysteresis input pin and it has a pull-up resistor available by mask option. the simplest reset circuit is connect reset pin with a capacitor to v ss and a diode to v dd . reset
23 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 EM73962 i/o port description : port input function output function note 0 e input port , wakeup function 1-- -- 2-- -- 3 -- i p3(1..0) : rom bank selection 4 e input port e output port, p4.0/sound 5-- -- 6-- -- 7-- -- 8 e input port, wakeup function, e output port external interrupt input 9 -- i p9.3 : ram bank selection 10 -- -- 11 -- -- 12 -- -- 13 -- -- 14 -- -- 15 -- -- 16 i sleep/hold mode control register 17 i sound effect volume control register 18 -- 19 -- 20 -- 21 -- 22 -- 23 i sound effect frequency register low nibble 24 i sound effect command register high nibble 25 i timebase control register 26 -- 27 i lcd control register 28 i timer/counter a control register 29 i timer/counter b control register 30 i sound effect command register 31 --
24 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 absolute maximum ratings items sym. ratings conditions supply voltage v dd -0.5v to 6v input voltage v in -0.5v to v dd +0.5v output voltage v o -0.5v to v dd +0.5v power dissipation p d 300mw t opr =50 c operating temperature t opr 0 c to 50 c storage temperature t stg -55 c to 125 c dc electrical characteristics (v dd =3 0.3v, v ss =0v, t opr =25 c) parameters sym. min. typ. max. unit conditions supply current i dd - 0.7 2 ma v dd =3.3v,no load,fc=4mhz (rc osc : r=6.2k w , c=20pf) - 0.1 1 m av dd =3.3v, sleep mode hysteresis voltage v hys+ 0.5v dd - 0.75v dd v reset, p0, p8 v hys- 0.2v dd - 0.4v dd v input current i ih -- 1 m a p0, reset, v dd =3.3v,v ih =3.3/0v -- 1 m a open-drain, v dd =3.3v,v ih =3.3/0v i il - - -500 m a push-pull, v dd =3.3v ,v il =0.4v,except p4 output voltage v oh 2.4 - - v push-pull, v dd =2.7v,p4(high current pmos), sound,i oh =-0.9ma 2.0 - - v push-pull, v dd =2.7v,others,i oh =-40 m a v ol - - 0.3 v v dd =2.7v,i ol =0.9ma leakage current i lo -- 1 m a open-drain, v dd =3.3v, v o =3.3v input resistor r in 100 200 300 k w p0 300 600 900 k w reset frequency stability - 15 - % fc=4mhz,rc osc,[f(3v)-f(2.4v)]/f(3v) frequency variation - 20 - % fc=4mhz, v dd =3v,rc osc, [f(typical)-f(worse case)]/f(typical) recommanded operating conditions items sym. ratings condition supply voltage v dd 2.4v to 5.0v input voltage v ih 0.90xv dd to v dd v il 0v to 0.10xv dd operating frequency f c 480k to 4mhz clk (rc osc) 480k to 4.19mhz xin,xout (crystal osc)
25 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 (v dd =4.5 0.5v, v ss =0v, t opr =25 c) parameters sym. min. typ. max. unit conditions supply current i dd - 4.5 5.5 ma v dd =5v, no load,fc=4.19mhz(crystal osc) - 1.5 2 ma v dd =5v, no load,fc=4mhz(rc osc : r=7.5k w , c=20pf) - 0.1 1 m av dd =5v, sleep mode hysteresis voltage v hys+ 0.5v dd - 0.75v dd v reset, p0, p8 v hys- 0.2v dd - 0.4v dd v input current i ih -- 1 m a p0, reset, v dd =5v,v ih =5/0v -- 1 m a open-drain, v dd =5v,v ih =5/0v i il - - -1 ma push-pull, v dd =5v ,v il =0.4v,except p4 output voltage v oh 3.0 - - v push-pull, p4(high current pmos),sound v dd =4v, i oh =-4ma 2.4 - - v push-pull, p4(low current pmos),p8 v dd =4v, i oh =-200 m a v ol - - 1.0 v v dd =4v, i ol =4ma leakage current i lo -- 1 m a open-drain, v dd =5v, v o =5v input resistor r in 30 90 150 k w p0 100 300 450 k w reset frequency stability - 10 - % fc=4mhz,rc osc,[f(4.5v)-f(3.6v)]/f(4.5v) frequency variation - 20 - % fc=4mhz, v dd =4.5v,rc osc, [f(typical)-f(worse case)]/f(typical)
26 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 reset pin type type reset-a reset mask option xin xout crystal osc. mask option : mask option p0/wakeup type input-a clk wakeup function mask option rc osc. (comparator) type i/o output data latch input data output data path b path a sel special function control input wakeup function mask option oscillation pin type type osc-a type osc-c input pin type type input-a type input-b i/o pin type type i/o type i/o-l
27 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 type i/o-n type i/o-o path a : for set and clear bit of port instructions, data goes through path a from output data latch to cpu. path b : for input and test instructions, data from output pin go through path b to cpu and the output data latch will be set to high. input data output data path b path a type i/o-n output data latch special function output : mask option : mask option
28 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 pad diagram chip size : 2870 x 2830 m m pad no. symbol x y 1 p4.2 -1267.3 -147.3 2 p4.3 -1267.3 -301.4 3 com7 -1269.4 -448.7 4 com6 -1269.4 -576.8 5 com5 -1269.4 -704.9 6 com4 -1269.4 -833.0 7 com3 -1269.4 -961.1 8 com2 -1269.4 -1089.2 9 com1 -1269.4 -1217.3 10 com0 -773.7 -1249.4 11 seg39 -645.6 -1249.4 12 seg38 -517.5 -1249.4 13 seg37 -389.4 -1249.4 14 seg36 -261.3 -1249.4 15 seg35 -133.2 -1249.4 16 seg34 -5.1 -1249.4 17 seg33 123.0 -1249.4 18 seg32 251.1 -1249.4 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 test reset xin xout vdd sound p4.0 p4.1 p4.2 p4.3 com7 com6 com5 com4 com3 com2 com1 com0 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 vrlc p0.3 p0.2 p0.1 p0.0 p8.3 p8.2 p8.1 p8.0 vss seg0 seg1 seg2 seg3 seg4 (0,0) EM73962
29 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 pad no. symbol x y 19 seg31 379.2 -1249.4 20 seg30 507.3 -1249.4 21 seg29 635.4 -1249.4 22 seg28 763.5 -1249.4 23 seg27 891.6 -1249.4 24 seg26 1019.7 -1249.4 25 seg25 1147.8 -1249.4 26 seg24 1275.9 -1249.4 27 seg23 1266.8 -1041.0 28 seg22 1266.8 -912.9 29 seg21 1266.8 -784.8 30 seg20 1266.8 -656.7 31 seg19 1266.8 -528.6 32 seg18 1266.8 -400.5 33 seg17 1266.8 -272.4 34 seg16 1266.8 -144.3 35 seg15 1266.8 -16.2 36 seg14 1266.8 111.9 37 seg13 1266.8 240.0 38 seg12 1266.8 368.1 39 seg11 1266.8 496.2 40 seg10 1266.8 624.3 41 seg9 1266.8 752.4 42 seg8 1266.8 880.5 43 seg7 1266.8 1008.6 44 seg6 1266.8 1136.7 45 seg5 1266.8 1264.8 46 seg4 708.6 1250.8 47 seg3 580.5 1250.8 48 seg2 452.4 1250.8 49 seg1 324.3 1250.8 50 seg0 196.2 1250.8 51 vss 58.6 1235.8 52 p8.0 -101.3 1250.8 53 p8.1 -229.6 1250.8 54 p8.2 -363.0 1250.8 55 p8.3 -491.2 1250.8 56 p0.0 -624.6 1250.8 57 p0.1 -752.9 1250.8 58 p0.2 -886.3 1250.8 59 p0.3 -1014.5 1250.8 60 vrlc -1145.3 1250.8 61 test -1276.1 1250.8 62 reset -1269.6 1032.4 63 xin -1225.5 854.4 64 xout -1224.6 643.4
30 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 pad no. symbol x y 65 vdd -1249.3 472.4 66 sound -1268.0 311.8 67 p4.0 -1267.3 160.7 68 p4.1 -1267.3 6.7
31 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 instruction table (1) data transfer mnemonic object code ( binary ) operation description byte cycle flag cz s lda x 0110 1010 xxxx xxxx acc ? ram[x] 2 2 - z 1 ldam 0101 1010 acc ? ram[hl] 1 1 - z 1 ldax 0110 0101 acc ? rom[dp] l 12-z1 ldaxi 0110 0111 acc ? rom[dp] h ,dp+1 1 2 - z 1 ldh #k 1001 kkkk hr ? k11--1 ldhl x 0100 1110 xxxx xx00 lr ? ram[x],hr ? ram[x+1] 2 2 - - 1 ldia #k 1101 kkkk acc ? k11-z1 ldl #k 1000 kkkk lr ? k11--1 sta x 0110 1001 xxxx xxxx ram[x] ? acc 2 2 - - 1 stam 0101 1001 ram[hl] ? acc 1 1 - - 1 stamd 0111 1101 ram[hl] ? acc, lr-1 1 1 - z c stami 0111 1111 ram[hl] ? acc, lr+1 1 1 - z c' std #k,y 0100 1000 kkkk yyyy ram[y] ? k22--1 stdmi #k 1010 kkkk ram[hl] ? k, lr+1 1 1 - z c' tha 0111 0110 acc ? hr 1 1 - z 1 tla 0111 0100 acc ? lr 1 1 - z 1 (2) rotate mnemonic object code ( binary ) operation description byte cycle flag czs rlca 0101 0000 ? cf ? acc ? 11czc' rrca 0101 0001 ? cf ? acc ? 11czc' ( 3) arithmetic operation mnemonic object code ( binary ) operation description byte cycle flag c zs adcam 0111 0000 acc ? acc + ram[hl] + cf 1 1 c z c' add #k,y 0100 1001 kkkk yyyy ram[y] ? ram[y] +k 2 2 - z c' adda #k 0110 1110 0101 kkkk acc ? acc+k 2 2 - z c' addam 0111 0001 acc ? acc + ram[hl] 1 1 - z c' addh #k 0110 1110 1001 kkkk hr ? hr+k 2 2 - z c' addl #k 0110 1110 0001 kkkk lr ? lr+k 2 2 - z c' addm #k 0110 1110 1101 kkkk ram[hl] ? ram[hl] +k 2 2 - z c' deca 0101 1100 acc ? acc-1 1 1 - z c decl 0111 1100 lr ? lr-1 1 1 - z c decm 0101 1101 ram[hl] ? ram[hl] -1 1 1 - z c inca 0101 1110 acc ? acc + 1 1 1 - z c'
32 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 incl 0111 1110 lr ? lr + 1 1 1 - z c' incm 0101 1111 ram[hl] ? ram[hl]+1 1 1 - z c' suba #k 0110 1110 0111 kkkk acc ? k-acc 2 2 - z c sbcam 0111 0010 acc ? ram[hll - acc - cf' 1 1 c z c subm #k 0110 1110 1111 kkkk ram[hl] ? k - ram[hl] 2 2 - z c ( 4) logical operation mnemonic object code ( binary ) operation description byte cycle flag czs anda #k 0110 1110 0110 kkkk acc ? acc&k 2 2 - z z' andam 0111 1011 acc ? acc & ram[hl] 1 1 - z z' andm #k 0110 1110 1110 kkkk ram[hl] ? ram[hl]&k 2 2 - z z' ora #k 0110 1110 0100 kkkk acc ? acc k 2 2 - z z' oram 0111 1000 acc ? acc ram[hl] 1 1 - z z' orm #k 0110 1110 1100 kkkk ram[hl] ? ram[hl] k 2 2 - z z' xoram 0111 1001 acc ? acc^ram[hl] 1 1 - z z' (5) exchange mnemonic object code ( binary ) operation description byte cycle flag czs exa x 0110 1000 xxxx xxxx acc ? ram[x] 2 2 - z 1 exah 0110 0110 acc ? hr 1 2 - z 1 exal 0110 0100 acc ? lr 1 2 - z 1 exam 0101 1000 acc ? ram[hl] 1 1 - z 1 exhl x 0100 1100 xxxx xx00 lr ? ram[x], hr ? ram[x+1] 2 2 - - 1 (6) branch mnemonic object code ( binary ) operation description byte cycle flag czs sbr a 00aa aaaa if sf=1 then pc ? pc 12-6 .a 5-0 11--1 else null lbr a 1100 aaaa aaaa aaaa if sf= 1 then pc ? a else null 2 2 - - 1 slbr a 0101 0101 1100 aaaa if sf=1 then pc ? a else null 3 3 - - 1 aaaa aaaa (a:1000~1fffh) 0101 0111 1100 aaaa aaaa aaaa (a:0000~0fffh) (7) compare mnemonic object code ( binary ) operation description byte cycle flag czs cmp #k,y 0100 1011 kkkk yyyy k-ram[y] 2 2 c z z' cmpa x 0110 1011 xxxx xxxx ram[x]-acc 2 2 c z z' - - - - - -
33 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 (8) bit manipulation mnemonic object code ( binary ) operation description byte cycle flag czs clm b 1111 00bb ram[hl] b ? 011--1 clp p,b 0110 1101 11bb pppp port[p] b ? 022--1 clpl 0110 0000 port[lr 3-2 +4] lr 1-0 ? 012--1 clr y,b 0110 1100 11bb yyyy ram[y] b ? 022--1 sem b 1111 01bb ram[hl] b ? 111--1 sep p,b 0110 1101 01bb pppp port[p] b ? 122--1 sepl 0110 0010 port[lr 3-2 +4] lr l-0 ? 112 --1 set y,b 0110 1100 01bb yyyy ram[y] b ? 122--1 tf y,b 0110 1100 00bb yyyy sf ? ram[y] b '22--* tfa b 1111 10bb sf ? acc b '11--* tfm b 1111 11bb sf ? ram[hl] b '11--* tfp p,b 0110 1101 00bb pppp sf ? port[p] b '22--* tfpl 0110 0001 sf ? port[lr 3-2 +4] lr 1-0 '1 2--* tt y,b 0110 1100 10bb yyyy sf ? ram[y] b 22--* ttp p,b 0110 1101 10bb pppp sf ? port[p] b 22--* (9) subroutine mnemonic object code ( binary ) operation description byte cycle flag czs lcall a 0100 0aaa aaaa aaaa stack[sp] ? pc, 2 2 - - - sp ? sp -1, pc ? a scall a 1110 nnnn stack[sp] ? pc, 1 2 - - - sp ? sp - 1, pc ? a, a = 8n + 6 (n =1~15 ),0086h (n = 0) ret 0100 1111 sp ? sp + 1, pc ? stack[sp] 1 2 - - - (10) input/output mnemonic object code ( binary ) operation description byte cycle flag czs ina p 0110 1111 0100 pppp acc ? port[p] 2 2 - z z' inm p 0110 1111 1100 pppp ram[hl] ? port[p] 2 2 - - z' out #k,p 0100 1010 kkkk pppp port[p] ? k22--1 outa p 0110 1111 000p pppp port[p] ? acc 2 2 - - 1 outm p 0110 1111 100p pppp port[p] ? ram[hl] 2 2 - - 1 mnemonic object code ( binary ) operation description byte cycle flag czs cmpam 0111 0011 ram[hl] - acc 1 1 c z z' cmph #k 0110 1110 1011 kkkk k - hr 2 2 - z c cmpia #k 1011 kkkk k - acc 1 1 c z z' cmpl #k 0110 1110 0011 kkkk k-lr 2 2 - z c
34 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 mnemonic object code ( binary ) operation description byte cycle flag czs tfcfc 0101 0011 sf ? cf', cf ? 0110-* ttcfs 0101 0010 sf ? cf, cf ? 1111-* tzs 0101 1011 sf ? zf 1 1 - - * (12) interrupt control mnemonic object code ( binary ) operation description byte cycle flag czs cil r 0110 0011 11rr rrrr il ? il & r 2 2 - - 1 dicil r 0110 0011 10rr rrrr eif ? 0,il ? il&r 2 2 - - 1 eicil r 0110 0011 01rr rrrr eif ? 1,il ? il&r 2 2 - - 1 exae 0111 0101 mask ? acc 1 1 - - 1 rti 0100 1101 sp ? sp+1,flag.pc 1 2 * * * ? stack[sp],eif ?1 (13) cpu control mnemonic object code ( binary ) operation description byte cycle flag czs nop 0101 0110 no operation 1 1 - - - (14) timer/counter & data pointer & stack pointer control mnemonic object code ( binary ) operation description byte cycle flag czs ldadpl 0110 1010 1111 1100 acc ? [dp] l 22-z1 ldadpm 0110 1010 1111 1101 acc ? [dp] m 22-z1 ldadph 0110 1010 1111 1110 acc ? [dp] h 22-z1 ldasp 0110 1010 1111 1111 acc ? sp 2 2 - z 1 ldatal 0110 1010 1111 0100 acc ? [ta] l 22-z1 ldatam 0110 1010 1111 0101 acc ? [ta] m 22-z1 ldatah 0110 1010 1111 0110 acc ? [ta] h 22 -z1 ldatbl 0110 1010 1111 1000 acc ? [tb] l 22-z1 ldatbm 0110 1010 1111 1001 acc ? [tb] m 22-z1 ldatbh 0110 1010 1111 1010 acc ? [tb] h 22-z1 stadpl 0110 1001 1111 1100 [dp] l ? acc 2 2 - - 1 stadpm 0110 1001 1111 1101 [dp] m ? acc 2 2 - - 1 stadph 0110 1001 1111 1110 [dp] h ? acc 2 2 - - 1 stasp 0110 1001 1111 1111 sp ? acc 2 2 - - 1 statal 0110 1001 1111 0100 [ta] l ? acc 2 2 - - 1 statam 0110 1001 1111 0101 [ta] m ? acc 2 2 - - 1 statah 0110 1001 1111 0110 [ta] h ? acc 2 2 - - 1 statbl 0110 1001 1111 1000 [ tb] l ? acc 2 2 - - 1 statbm 0110 1001 1111 1001 [tb] m ? acc 2 2 - - 1 statbh 0110 1001 1111 1010 [tb] h ? acc 2 2 - - 1 (11) flag manipulation
35 * this specification are subject to be changed without notice. EM73962 4-bit microcontroller 7.17.1998 **** symbol description symbol description symbol description hr h register lr l register pc program counter dp data pointer sp stack pointer stack[sp] stack specified by sp a cc accumulator flag all flags cf carry flag zf zero flag sf status flag ei enable interrupt register il interrupt latch mask interrupt mask port[p] port ( address : p ) ta timer/counter a tb timer/counter b ram[hl] data memory (address : hl ) ram[x] data memory (address : x ) rom[dp] l low 4-bit of program memory rom[dp] h high 4-bit of program memory [dp] l low 4-bit of data pointer register [dp] m middle 4-bit of data pointer register [dp] h high 4-bit of data pointer register [ta] l ([tb] l ) low 4-bit of timer/counter a [ta] m ([tb] m ) middle 4-bit of timer/counter a (timer/counter b) register (timer/counter b) register [ta] h ([tb] h ) high 4-bit of timer/counter a lr 1 -0 contents of bit assigned by bit (timer/counter b) register 1 to 0 of lr lr 3-2 bit 3 to 2 of lr a 5-0 bit 5 to 0 of destination address for branch instruction pc 12-6 bit 12 to 6 of program counter ? transfer ? exchange + addition - substraction & logic and logic or ^ logic xor inverse operation . concatenation #k 4-bit immediate data x 8-bit ram address y 4-bit zero-page address p 4-bit or 5-bit port address b bit address r 6-bit interrupt latch - -

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